Vendredi 12 Septembre 2025
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Towards effective hardware implementation of compressed caches
André Seznec (currently SiFive) will present his journey into hardware compression on Friday 12th, at 10AM in Amphi Barbillon (Grenoble INP, 46 Avenue Félix Viallet, south entrance then left). Talk (approx 1h) will be in english or french based on who attends.
Abstract:
Towards effective hardware implementation of compressed caches. The cache hierarchy has been one of the key performance enablers of microprocessors for the last 40 years. In the 90's, I did participate to this adventure with the proposition of the skewed associative cache and the decoupled sectored cache. They influenced several industrial designs and inspired many derived academic studies. However I also worked (more recently) on compressed caches.
In this presentation, I will present my journey in research on compressed caches from 2014 to 2018. We proposed a complete solution for designing compressed caches: YACC an efficient and cost effective layout, DISH an efficient compression scheme that leverages YACC, and SRC an efficient replacement policy that leverages YACC and DISH. One of the frustrations in my career is that, to the best of my knowledge, such compressed caches have not appeared so far in any main stream design.
Bio:
André Seznec received his PhD in computer sciences from University of Rennes I in France.
In 1986, he joined INRIA, the French national research agency in computer science. Apart from a sabbatical in industry in 1999-2000, he spent most of his career at IRISA/INRIA Rennes and was promoted as a Fellow Research Director (DR0) in 2012. For the last few years, he has joined industry as an Intel Fellow (2021-2024), then a SiFive Fellow starting in 2024.
André Seznec has focused his research on processor architecture since the beginning of his Ph.D. thesis in 1983. His early contributions were on vector architectures, particularly the memory system. Since the beginning of the 1990s his main research activity has been focused on the architecture of microprocessors, including caches, pipeline, branch predictors, speculative execution, multithreading and multicores. Most members of the microarchitecture research community immediately identify André Seznec as the inventor of the TAGE branch predictor and of the skewed associative cache. His research has influenced the design of many high-end industrial microprocessors, particularly the caches and the branch predictors.
André Seznec has been the leader of compiler and architecture research groups, CAPS then ALF, at IRISA/INRIA from 1994 to 2016. For his work on caches and predictors, he received the Intel Research Impact Medal in 2012, the 2019 Intel Outstanding Researcher award and he was elevated to IEEE Fellow (2013) and ACM Fellow (2016). He received the 2020 IEEE CS B. Ramakrishna Rau Award and the 2025 ACM-IEEE CS Eckert-Mauchly award.
In 1986, he joined INRIA, the French national research agency in computer science. Apart from a sabbatical in industry in 1999-2000, he spent most of his career at IRISA/INRIA Rennes and was promoted as a Fellow Research Director (DR0) in 2012. For the last few years, he has joined industry as an Intel Fellow (2021-2024), then a SiFive Fellow starting in 2024.
André Seznec has focused his research on processor architecture since the beginning of his Ph.D. thesis in 1983. His early contributions were on vector architectures, particularly the memory system. Since the beginning of the 1990s his main research activity has been focused on the architecture of microprocessors, including caches, pipeline, branch predictors, speculative execution, multithreading and multicores. Most members of the microarchitecture research community immediately identify André Seznec as the inventor of the TAGE branch predictor and of the skewed associative cache. His research has influenced the design of many high-end industrial microprocessors, particularly the caches and the branch predictors.
André Seznec has been the leader of compiler and architecture research groups, CAPS then ALF, at IRISA/INRIA from 1994 to 2016. For his work on caches and predictors, he received the Intel Research Impact Medal in 2012, the 2019 Intel Outstanding Researcher award and he was elevated to IEEE Fellow (2013) and ACM Fellow (2016). He received the 2020 IEEE CS B. Ramakrishna Rau Award and the 2025 ACM-IEEE CS Eckert-Mauchly award.
Date et lieu
Vendredi 12 Septembre à 10:00
Amphi Barbillon (Grenoble INP)
Organisé par
Fabrice Rastello
Responsable de l'équipe CORSE
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